AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoA

Paper PS2-MoA2
Investigation of Gate Oxide Behavior during Highly Selective Poly-Si Gate Etching for Triple Gate Transistors

Monday, October 31, 2005, 2:20 pm, Room 304

Session: Silicon Etching
Presenter: D. Kim, Samsung Electronics, South Korea
Authors: D. Kim, Samsung Electronics, South Korea
H.S. Lee, Samsung Electronics, South Korea
S.J. Park, Samsung Electronics, South Korea
Y.J. Jee, Samsung Electronics, South Korea
K.K. Chi, Samsung Electronics, South Korea
C.J. Kang, Samsung Electronics, South Korea
H.K. Cho, Samsung Electronics, South Korea
J.T. Moon, Samsung Electronics, South Korea
Correspondent: Click to Email
Triple gate transistor, or FinFET, is one of the most promising candidates for the next CMOS technology. FinFETs have better capability for higher transistor current and better controllability for the short channel effect, especially for sub 50nm ULSI devices. However, focusing on the fabrication aspects, the structure of FinFET has difficulties to overcome, which are inherently originated from using the fin-shaped active structure: (1) The thin gate oxide should be able to stand for the large amount of gate poly-Si etching not to leave any residues on the sidewalls and the bottom area of the 3-dimensional fin structure. (2) We should also overcome the undercut or tapering of the gate profile on the top and sidewall of the active area, which also originate from the 3-dimensional fin structure. These directly affect transistor characteristics such as threshold voltage distribution. In this work, we report detailed analyses on highly selective poly-Si gate etching for a FinFET. Since poly-Si etching should be carried out to the bottom area of the fin with G-ox exposed to the etch environment, high etch selectivity to G-ox is required. From this point of view, we tried to fully figure out how initial G-ox is affected by polymer deposition on G-ox, etching of G-ox itself, and plasma oxidation of silicon beneath the G-ox, which compete with one another during the gate etching. Transmission Electron Microscope (TEM) analysis, G-ox wet etch rate measurement, and measurement of electrical characteristics such as density of interface trap, charge density, leakage current were implemented. Based on the above investigations, plasma oxidation is considered to play an important role in gate etching with thin G-ox. It is also shown that the silicon-containing byproduct during gate etching is indispensable for polymer generation.