AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS2-MoA

Paper PS2-MoA1
Advanced Gate Stack Etch Modeling for 65 nm Node

Monday, October 31, 2005, 2:00 pm, Room 304

Session: Silicon Etching
Presenter: P.J. Stout, Freescale Semiconductor, Inc.
Authors: P.J. Stout, Freescale Semiconductor, Inc.
M. Shroff, Freescale Semiconductor, Inc.
T. Stephens, Freescale Semiconductor, Inc.
J.E. Vasek, Freescale Semiconductor, Inc.
O.O. Adetutu, Freescale Semiconductor, Inc.
S. Rauf, Freescale Semiconductor, Inc.
P. Ventzek, Freescale Semiconductor, Inc.
Correspondent: Click to Email
A reactor/feature modeling approach has been applied to etching an advanced gate stack. The reactor model is HPEM (developed at the University of Illinois) and the feature model is Papaya (developed at Freescale). Papaya is a 2D/3D Monte Carlo based feature scale model. The reactor model supplies Papaya with the identity, flux rate, angular distribution, and energy distribution of specie incident on the feature surface. Papaya has also been coupled to lithography models to obtain the initial resist profile used as a mask during the etch process. The gate stack consists of polysilicon, an anti-reflective coating, and a hard mask. Discussed will be the 3D feature modeling of the plasma etch steps required to etch through the gate stack. The cummulative effect of the gate etch steps is studied. The influence each etch step has on subsequent steps will be explored. The photoresist profile and feature proximity effects on the final polysilicon profile will also be discussed.