AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS1-MoA

Paper PS1-MoA1
Reduction of Line Edge Roughness for 65nm Technology Node for Etched Contact Holes

Monday, October 31, 2005, 2:00 pm, Room 302

Session: Dielectric Etch I
Presenter: B. Goodlin, Texas Instruments Incorporated
Authors: B. Goodlin, Texas Instruments Incorporated
D. Farber, Texas Instruments Incorporated
T. Lii, Texas Instruments Incorporated
G. Shinn, Texas Instruments Incorporated
Correspondent: Click to Email
For the 65nm technology node, reduction of contact hole line edge roughness is critical for reliable performance in densely packed memory cells. Origins of contact line edge roughness are attributable to three different mechanisms: 1) pattern transfer line edge roughness, resulting from propagation of striations from 193nm resist to the underlying substrate, 2) deposition-related line edge roughness, resulting from pattern transfer of non-uniform and irregular shaped deposition at the top of the hole to the bottom of the etched feature, and 3) pin-hole punch-through line edge roughness, where faceting or thinning of resist towards the end of etch processing results in shallow pin-holes that do not propagate down the entire length of the feature being etched. In order to fully appreciate these different types of line edge roughening for process optimization, a metrology technique was utilized that could characterize roughness at both the top and bottom of an etched feature. Using such metrology, an etch process has been optimized to minimize line edge roughness, while satisfying several other strict processing constraints.