We present requirements and methods for improvement of performance in low-k dielectric integrations using various etch and ash processes in back end of line applications. The correct etch and ash chemistry is the key to minimizing surface modifications. The use of porous ultra low-k materials is required to achieve an ultra low keff stack. These materials present new challenges to etch and ash engineers due to their low mechanical strength, porous nature and propensity to plasma damage. Plasma Etch and strip processes cause modifications to the dielectric that reduce the effectiveness of the low-k material. It will be necessary to pick materials with minimal chemical susceptibility to damage, and to develop new etch, ash and cleans processes that cause less damage. We use two layer metal test vehicles. A 90nm CVD (k=2.5) and a 130nm "late poragen burn-out" low-k (k=2.1). This paper presents a discussion on the stack integrations and the etch/ash approaches for each. Both integrations are VFTL (via first, trench last) with no embedded stop layers. Smooth etch fronts through etch and ash steps are key to the integrity of the metal barrier and to reliability performance. We will show the etch and ash chemistries required for each low-k and methods to control plasma damage to the low-k. Polymer deposition and its removal are controlling factors in damage control in the etch/ash processes. An investigation of effects from ash chemistries and reactors for plasma damage and impact on profiles will be presented. Interactions between processes, and their impact on the resulting profiles, will be given. Hardmask chemistries are particularly damaging & methods to damage reduction in these etches will be shown. Data will be presented on the rates and ash rates for ULK materials and the impact of the same process on plasma damage. It is shown that the ash process can be used to smooth the etch front to provide a smoother etch front.