AVS 52nd International Symposium
    Plasma Science and Technology Tuesday Sessions
       Session PS-TuA

Paper PS-TuA1
A New Wafer Level Micro Arcing Mechanism in 90nm CVD Low-K Via Etch on 300mm SOI Substrate

Tuesday, November 1, 2005, 2:00 pm, Room 302

Session: Dielectric Etch II
Presenter: H. Cong, Chartered Semiconductor MFG Ltd, Singapore
Authors: H. Cong, Chartered Semiconductor MFG Ltd, Singapore
C. Low, Chartered Semiconductor MFG Ltd, Singapore
R.P. Yelehanka, Chartered Semiconductor MFG Ltd, Singapore
X. Zhang, Chartered Semiconductor MFG Ltd, Singapore
C. Perera, Chartered Semiconductor MFG Ltd, Singapore
W. Liu, Chartered Semiconductor MFG Ltd, Singapore
J.B. Tan, Chartered Semiconductor MFG Ltd, Singapore
L.C. Hsia, Chartered Semiconductor MFG Ltd, Singapore
Correspondent: Click to Email
As semiconductor industry moves to 300mm platform and 90nm technologies and beyond, wafer level micro arcing (WLMA) becomes more frequent in dielectric etch. In this paper, we describe the finding of a new WLMA mechanism and the process regime optimization to prevent it happening. In SICOH via etch, high polymer chemistry is needed for better selectivity to both photo resist and underneath barrier. But on the other hand, a high ion energy plasma is required to achieve a good process widow. The etching tool we used is a 300mm capacitively coupled plasma (CCP) high-gap reactor, which has 60Mhz and 2Mhz RF power source applied on top and bottom electrode individually. During our initial via etch process development, C@sub4@F@sub6@/CH@sub3@F etc.were used as via main etch chemistry for better PR selectivity and striation performance. However, we occasionally encountered WLMA at wafer edge around guard rings. Bare Si wafer was used to check RF parameters during the etch process. Spikes were occasionally observed on lower Vpp and C@sub2@ position traces at the beginning of over etch step. We found that there was a powdery polymer deposited on the upper electrode after main etch step and the plasma instability is irrelevant to incoming material. This WLMA phenomenon is different from the experience on MERIE or CCP low-gap reactor. Therefore, we propose a new WLMA mechanism. In SIOCH via etch, main etch step chemistry generates heavy non-uniform polymer deposition on upper electrode. When the process switches to over etch step (normally high DC bias), the polymer out gassing from upper electrode will introduce non-uniformity e-field in the plasma and it triggers WLMA. New main etch chemistry was developed and proved successful for production. We also compared RF parameters during via etch on both SOI and bulk Si substrate, there is no significant difference with new developed recipe. Wafer full map electrical and KLA defect scanned results show free of WLMA.