AVS 52nd International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS-MoP

Paper PS-MoP16
Etching of Narrow Porous SiOCH Trenches using a TiN Metallic Hard Mask

Monday, October 31, 2005, 5:00 pm, Room Exhibit Hall C&D

Session: Plasma Science and Technology Poster Session
Presenter: M. Darnon, CNRS LTM - France
Authors: M. Darnon, CNRS LTM - France
N. Posseme, ST Microelectronics - France
D. Eon, UJF - France
T. David, CEA LETI - France
T. Chevolleau, CNRS LTM - France
L. Vallier, CNRS LTM - France
O. Joubert, CNRS LTM - France
Correspondent: Click to Email
In CMOS technology, most of the interlayer dielectric materials achieve low k values by introducing porosity in order to reduce the total resistance capacitance (RC) delay in the interconnect levels. Trench or via patterns are transferred into porous SiOCH (p-SiOCH) using a dual hard mask strategy. This approach minimizes the porous low k degradation induced during ash plasma exposure. Different hard masks (metallic such as TiN or TaN and inorganic such as SiO@sub 2@ or SiC) are currently under investigation to pattern 65 nm trenches targeted for the 45 nm node. This work is dedicated to the analysis of the impact of a metallic hard mask used to pattern narrow porous SiOCH trenches etched in fluorocarbon based plasmas. The stack investigated is composed of 600 nm p-SiOCH, 40 nm SiO@sub 2@, 45 nm TiN and 100 nm photoresist (PR). The 200 mm wafers are patterned using direct ebeam lithography to achieve aggressive trenches dimensions down to 50 nm. After TiN opening and resist removal, the SiO@sub 2@ and p-SiOCH layers are etched in two different industrial etching chambers: either an inductive (ICP) or a capacitive (MERIE) plasma source. Chemical topography analyses by X Ray Photoelectron Spectroscopy (XPS) and ion mass spectroscopy show that the condensation of low volatile Ti based etch by-products on the trench sidewalls can generate severe profile distortions. The profile distortion is strongly minimized and even suppressed by increasing the wafer temperature from 20°C up to 60°C. The TiN hard mask consumption during the dielectric etch process can be reduced by using highly polymerizing chemistries which contributes to the formation of a fluorocarbon overlayer on top of the mask. The patterning of very narrow trenches reveals that one of the main issues is the faceting of TiN hard mask, leading to unacceptable profile distortions. The impact of the plasma parameters on the profile distortion of narrow trenches will be presented and discussed.