AVS 52nd International Symposium
    Plasma Science and Technology Thursday Sessions
       Session PS+MS-ThM

Paper PS+MS-ThM7
Computational Modeling of Process Induced Damage During Back End of Line Wafer Processing

Thursday, November 3, 2005, 10:20 am, Room 302

Session: Process Equipment Modeling
Presenter: S. Rauf, Freescale Semiconductor, Inc.
Authors: S. Rauf, Freescale Semiconductor, Inc.
M. Rasco, Freescale Semiconductor, Inc.
A. Haggag, Freescale Semiconductor, Inc.
R. Chatterjee, Freescale Semiconductor, Inc.
M. Moosa, Freescale Semiconductor, Inc.
K. Junker, Freescale Semiconductor, Inc.
P. Ventzek, Freescale Semiconductor, Inc.
Correspondent: Click to Email
A variety of back end of line (BEOL) processes can subject ultra-thin gate dielectrics in transistors to extremely large electric fields or currents. These processes include plasma etching, plasma enhanced deposition and electron beam treatment of low-@kappa@ dielectrics. A computational modeling infrastructure is described in this presentation that is being used to address process induced damage issues for BEOL microelectronics manufacturing processes. The model couples simulations of plasma etching and electron beam processes to an electrostatic model for charging of gate dielectric. The 2-dimensional models for capacitively and inductively coupled etching plasmas are fluid-based and take account of the detailed plasma chemistry of etching plasmas. The electron beam process is simulated using a 1-dimensional Monte Carlo model. The 2/3 dimensional electrostatic model solves the coupled set of Poisson equation and current continuity equation. Dielectric and semi-conducting properties of materials are taken into account in the electrostatic model using nonlinear electric-field dependant conductivity. Computational results show that, if the gate dielectric is exposed to current from the processing equipment, it charges up rapidly leading to dielectric breakdown. The structure of the transistor, materials surrounding the transistors (e.g., insulation layers) and area of charge collection antennas determine how much current flows through the gate dielectric and the consequent damage that occurs to it. Examples are used to illustrate how this modeling infrastructure is being used to help design BEOL processes and integrations.