AVS 52nd International Symposium
    Electronic Materials and Processing Wednesday Sessions
       Session EM-WeA

Paper EM-WeA10
Ni Diffusion Studies From NiSi/Hf-based High-K Dielectric Stack Into Si

Wednesday, November 2, 2005, 5:00 pm, Room 309

Session: Contacts to Semiconductors
Presenter: P. Zhao, University of Texas at Dallas
Authors: P. Zhao, University of Texas at Dallas
M.J. Kim, University of Texas at Dallas
B.E. Gnade, University of Texas at Dallas
R.M. Wallace, University of Texas at Dallas
Correspondent: Click to Email
Fully silicided NiSi has been studied as a metal gate electrode due to low resistivity, scability and work function tunability.@footnote 1,2,3@ However, there remain many challenges for the integration of NiSi metal gates, such as phase stability, incomplete silicidation and possible Ni diffusion. The interdiffusion of Ni from NiSi through dielectrics into the underlying Si substrate (channel) has not yet been reported in the literature to our knowledge. We have investigated the Ni diffusion from NiSi through SiO@sub X@N@sub Y@ and Hf-based gate dielectrics into the Si channel. SIMS profiles show that interdiffusion of Ni from NiSi through a 13Å SiO@sub X@N@sub Y@ into the Si channel can be observed after thermal anneal budgets even as low as 350°C for 60min, representative of a typical backend process. It is also found that the Ni penetration increases with temperature and time. Although the penetration is reduced for a stack with thicker HfSiON dielectrics (23Å), the diffusion is observed when the stack is annealed for 60min at 400°C. Compared to N@sub 2@ annealing, deuterated forming gas annealing appears to enhance the Ni penetration. Both backside and front side SIMS, XRD, and HRTEM results will be presented. The possible diffusion mechanism will be discussed. This work is supported by Texas Instruments and the Semiconductor Research Corporation. @FootnoteText@ @footnote 1@ Z. Krivokapic, W. Maszara, F. Arsnia, E. Patron, Y. Kim, L. Washington, et al., VLSI 2003, p. 131-132 (2003)@footnote 2@ J. Kedzierski, E. Nowak, T. Kanarsky, Y. Zhang, D. Boyd, R. Carruthers, et al., IEDM 2002, p.247-250 (2002)@footnote 3@ C. Cabral, Jr., J. Kedzierski, B. Linder, S. Zafar, V. Narayanan, S. Fang, A. Steegen, P. Kozlowski, R. Carruthers, and R. Jammy. 2004 Symposium on VLSI Technology Digest of Technical Papers, p.184-185 .