AVS 51st International Symposium
    Manufacturing Science and Technology Thursday Sessions
       Session MS-ThM

Paper MS-ThM7
DRAM Gate CD Control in Dry Etch Process using Optical Integrated Metrology

Thursday, November 18, 2004, 10:20 am, Room 303B

Session: Advanced Process Control
Presenter: Y.J. Jung, Samsung Electronics Co., LTD., Korea
Authors: Y.J. Jung, Samsung Electronics Co., LTD., Korea
Y.J. Kim, Samsung Electronics Co., LTD., Korea
G.J. Min, Samsung Electronics Co., LTD., Korea
C.J. Kang, Samsung Electronics Co., LTD., Korea
H.K. Cho, Samsung Electronics Co., LTD., Korea
J.-T. Moon, Samsung Electronics Co., LTD., Korea
J.W. Shon, Lam Research Corporation
Correspondent: Click to Email
In current CMOS technology, a traditional sequence to obtain a target post etch CD is to perform lithography patterning and measure the CD in resist followed by dry etch and strip process. There is a specification for the CD in resist, which may result in target post etch CD. After the measurement of the CD in resist by using in-line scanning electron microscope (SEM), it is determined whether the rework process of lithography is necessary or not to meet the specification of the CD in resist. This kind of traditional CD control sequence, however, may be a source of following problems. First, since the measurement of the CD in resist cannot be performed for every lot as well as every single wafer due to throughput in mass production environment, it is not sure that all lots and/or wafers meet the specification of the CD in resist. Second, rework process for out of specification requires additional time, resources, and cost, which result in the decrease of productivity. Third, the measurement of the CD in resist using SEM causes CD slimming, which may give uncertainty error in CD determination. Although CD control in dry etch process using the optical integrated metrology is one of the promising candidates to overcome the above problems, it has not been applied in the DRAM Gate etch process due to the difficulty in thick Si@sub 3@N@sub 4@ hard mask. In this work, DRAM gate CD control in dry etch process is applied to sub-100 nm transistor fabrication. Gate etch of Si@sub 3@N@sub 4@ hard mask is performed using dual-frequency capacitively coupled plasma (DF-CCP) type etcher. After the CD in resist for each wafer is measured using the optical integrated metrology, the process controller determines a proper process condition to meet the target post etch CD according to the predetermined model of CD control with the measured CD in resist. Throughout this CD control in DRAM gate etch process, the variation of CD in resist (@>=@10nm) is reduced dramatically (@<=@2nm).