AVS 50th International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS2-WeM

Paper PS2-WeM5
Selective Dry Etching of SrBi@sub 2@Ta@sub 2@O@sub 9@/CeO@sub 2@ in the High Density Inductively Coupled Plasma Reactive Ion Etching

Wednesday, November 5, 2003, 9:40 am, Room 315

Session: Etching Difficult Materials
Presenter: S.I. Shim, Korea University
Authors: S.I. Shim, Korea University
Y.S. Kwon, Korea Institute of Science and Technology
S.I. Kim, Korea Institute of Science and Technology
Y.T. Kim, Korea Institute of Science and Technology
J.H. Park, Korea University
Correspondent: Click to Email
The dry etching and etch stop of the ferroelectric film on the silicon surface without damage is the key process of the self-aligned gate structure for the fabrication of Single Transistor Type Ferroelectric Memory. The high vertical etching angle is also necessary for the high integration. In this paper, etching characteristics and selective dry etchings of SrBi@sub 2@Ta@sub 2@O@sub 9@ (SBT) film and CeO@sub 2@ film which is used for the buffer layer to improve the interface between SBT and silicon surface by using the Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE) system with various Ar/Cl@sub 2@ gas mixtures were reported. The highest etching selectivity of SBT/CeO@sub 2@ was 6.8 and the vertical angle of SBT was 82°. The samples for etch were prepared by depositing CeO2 films with the thickness of 200 Å on Silicon substrates using rf sputtering of a Ce target in the reactive oxygen ambient. The SBT films with the thickness of 3000 Å were prepared on the CeO@sub 2@ film and Si substrate by MOD method. The capacitor-voltage (C-V) measurement shows there was no degradation of the ferroelectric characteristics after dry etching process. The SEM images and XPS data proved the etch stop was achieved successfully. For further investigation, N+/P diode junction and the metal ferroelectric insulator semiconductor filed effect transistor (MFISFET) with Pt/SBT/CeO@sub 2@/Si gate structure were fabricated. The I-V characteristics of the N+/p junctions and the drain current-drain voltage (I@sub D@-V@sub D@) and drain current-gate voltage (I@sub D@-V@sub G@) characteristics of the fabricated MFISFET show the etch stop process by using ICP-RIE system was successfully achieved without damage of silicon surface and degradation of ferroelectric characteristics.