AVS 50th International Symposium
    Plasma Science and Technology Thursday Sessions
       Session PS2-ThM

Paper PS2-ThM9
Critical Issues in Dual Damascene Etch

Thursday, November 6, 2003, 11:00 am, Room 315

Session: Low k Dielectric Etch
Presenter: M. Hussein, Intel Corporation
Authors: M. Hussein, Intel Corporation
M. Heckscher, Intel Corporation
S. Suri, Intel Corporation
Correspondent: Click to Email
This work examines the critical etch issues facing dual damascene integration scheme for the 90nm technology node and beyond. Emphasis will be placed on selectivity needs during via and etch stop layer etch, in particular. We investigated etching chemistries containing fluorine, and fluorocarbon-generating radicals using 300mm wafer size substrate. We will present and discuss the impact of chemistry and etching system configuration on etch selectivity during via and etch stop layer etch. Attaining a manufacturable level of selectivity between silicon-based low-k ILDs and advanced etch stop layers, in spite of the similarities in composition and characteristics of these materials, is shown to be quite challenging.