AVS 50th International Symposium
    Plasma Science and Technology Thursday Sessions
       Session PS2-ThM

Paper PS2-ThM10
In-Situ Etch-Stop Etch for Cu/Low-k Damascene Etch Applications

Thursday, November 6, 2003, 11:20 am, Room 315

Session: Low k Dielectric Etch
Presenter: P. Jiang, Texas Instruments
Authors: P. Jiang, Texas Instruments
R. Kraft, Texas Instruments
E. Burke, Texas Instruments
Correspondent: Click to Email
An in-situ plasma etch process was developed for the 90nm technology in which damascene structures (vias or trenches) and their etch-stop layers are etched in a single chamber. The in-situ process sequence includes BARC opening, low-k dielectric (OSG) etch with high selectivity to etch-stop layer (SiC), and SiC etch-stop removal. This process has provided significant cost reduction and productivity benefits to the Cu single damascene integration schemes, due to fewer process steps and higher process yield. Preserving feature CDs and etch profiles for low-k dielectric etches with 193nm lithography is particularly challenging due to the poor etch resistance of 193nm resists and small CDs (<150nm). The in-situ process has reduced via etch CD bias by ~15nm as compared to the conventional ex-situ etch-stop etch. It has also eliminated via profile bowing induced typically by ex-situ etch-stop etch and post-etch cleans, and increased the selectivity of SiC to OSG by ~80% in the etch-stop etch step. More importantly, equivalent or better via yield was achieved with smaller CDs using the in-situ process, due to improved profiles. In this paper, we will discuss the development of in-situ etch-stop etch process for single damascene via etch. The detailed results about the process, and its impact on process and electrical performance will be reported.