AVS 50th International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS1-WeM

Paper PS1-WeM1
The Study of Plasma Etching Limits Using Nanometer-Scale Self-Assembled Arrays

Wednesday, November 5, 2003, 8:20 am, Room 314

Session: Plasma Processing of Nanostructures and Nanomaterials
Presenter: Y. Zhang, IBM
Authors: Y. Zhang, IBM
T.J. Dalton, IBM
Correspondent: Click to Email
Fine patterning of semiconductor nano-scale features at the sub-20nm region is a challenging task. Among the nanometer scale features of importance in microelectronics and bio-microelectronics applications are: (1) open standing nano-features, i.e., a Si gate, and (2) small nano holes, i.e., an array of vias with nanometer scale diameter. The rapid shrinking of conventional CMOS technology is quickly approaching a perceived scalability limit or "brick wall". Plasma etching of true nanometer scale features may also face its limits. For open standing nano-features, the main challenge (or soft limits) is CD control, e.g., line edge roughness (LER) control of sub-10nm Si gate lines. A LER tolerance of 10% for 10nm gates means controlling 1nm, which has about 1 layer of silicon atoms on each side of gates. For true nanometer scale via arrays, the diameter of the vias for sub-10nm sizes is approaching the sizes of reactive products, e.g., SiBr4, SiF4, and SiCl4. In this case, plasma etching may hit its ultimate limits ("hard" limits). In this study, self-assembled nanometer scale diblock copolymer arrays were used to generate large scale (across 200 mm wafers) sub-20 nanometer test structures. The nanometer hole arrays were used to tested plasma etching characteristics of different materials, i.e., silicon, silicon dioxide, and silicon nitride with different plasma chemistries, from fluorine, chlorine, to bromine to vary the sizes of reactive species, F, Cl, to Br, and etching byproducts, such as SiF4, SiCl4, to SiBr4, with the aim of finding the plasma etching limits. In this paper, we present our recent work on the challenges of pattering nano-features, e.g., decreasing patterning layer thickness, aspect ratio dependent etch (ARDE), selectivity, and limits for sub-10 nm scale holes. Underlying principle of the different etching chemistry and processing parameters and their advantage and drawback to etch nanometer scale features will be also discussed.