AVS 50th International Symposium
    Plasma Science and Technology Wednesday Sessions
       Session PS-WeP

Paper PS-WeP13
A Model of Feature Profile Evolution for Nanometer-Scale Control of Etched Profiles and Critical Dimensions

Wednesday, November 5, 2003, 11:00 am, Room Hall A-C

Session: Poster Session
Presenter: Y. Osano, Kyoto University, Japan
Authors: K. Ono, Kyoto University, Japan
Y. Osano, Kyoto University, Japan
A. Sano, Kyoto University, Japan
K. Takahashi, Kyoto University, Japan
Y. Setsuhara, Kyoto University, Japan
Correspondent: Click to Email

As integrated circuit device dimensions continue to be scaled down, increasingly strict requirements are being imposed on plasma etching technology. The precise control of etched profiles and critical dimensions (CDs) is still one of the most important issues to be addressed, particularly in gate etch processes. In developing the technology to meet these demands, the modeling or simulation is an attractive approach, which significantly contributes to optimize complex processes in the fabrication of microelectronic devices. This paper presents a model of the feature profile evolution for nanometer-scale control of the profile and CD during etching of poly-Si gate electrodes in high-density chlorine- and bromine-containing plasmas. The model employs a full matrix approach with the volume density function in the entire computational domain for the materials being etched. This approach enables us to take into account surface reaction processes of enormous complexity that would occur during etching, particularly multilayer adsorption or reaction kinetics on feature surfaces, which the usual string algorithm with Langmuir adsorption scheme is hard to deal with. The model includes the transport and surface reaction kinetics of ions and neutrals in microstructures, based on our present understanding: neutral adsorption, geometrical shadowing, surface reemission or reflection of ions and neutrals, localized charging of feature surfaces, purely chemical etching, physical sputtering, ion-assisted reactions, and surface inhibitor deposition. The numerical results indicated that a thin passivation layer of surface inhibitors on feature sidewalls, surface temperature, and charging of mask layers play a key role in achieving the nanometer-scale control in gate etch processes.