Dielectric etch has grown in importance during the last decade with the emergence of single- and dual-damascene processing for semiconductor interconnect structures utilizing copper metallurgy, first in research and development and now in high-volume manufacturing. At the same time, the challenges of dielectric etch for semiconductor processing have changed significantly due to two factors. First, the materials of interest have evolved from silicon dioxide to "dense" low dielectric constant ("low-k") materials (both organic and silicate) to porous low-k materials (again, both organic and silicate). Second, the critical dimension (CD) has decreased to the sub 100-nm regime, forcing extreme control of feature sizes and sidewall profiles. This talk will focus on the evolution of dielectric etch for advanced logic integrated circuit fabrication in the last decade, specifically discussing dielectric materials, etch processes, and etching sources. Additionally, we will look ahead to issues with dielectric etch in the future.