AVS 50th International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM8
Investigation of Trim Etching Process for Formation of Si/High-K Gate Stack

Monday, November 3, 2003, 10:40 am, Room 315

Session: Critical Dimension Etching
Presenter: K.M. Tan, National University of Singapore
Authors: K.M. Tan, National University of Singapore
W.J. Yoo, National University of Singapore
L. Chan, Chartered Semiconductor Manufacturing, Singapore
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In recent years, a photoresist trimming technique based on the current 248nm and 193nm lithography technology are being developed to achieve smaller gates. In this work, we investigated the trimming technique to directly apply to the etching of the Si/SiO@sub 2@ and Si/HfO@sub 2@ gate stacks to further reduce the gate length. The trimming process developed using an industry standard ICP etcher consists of a main etch step followed by a trimming step using HBr, SF@sub 6@ and Cl@sub 2@. When HBr and SF@sub 6@ were used, a Si layer was trimmed at the rate of 17nm per minute at a pressure of 80mTorr, a bias power of 60W and an inductive power of 400W. A higher trim rate was obtained by using a higher inductive power and also by replacing HBr with Cl@sub 2@. However, the use of Cl@sub 2@ resulted in the decrease of the selectivity of Si to the underlying SiO@sub 2@, and thus reduced the maximum allowable trimming time. The trimming rate varied with pressure with an initial increase from 40mTorr to 70mTorr and a subsequent decrease from 70mTorr to 80mTorr. According to the results obtained for all the etch conditions used, HfO@sub 2@ produced a much slower etch rate than SiO@sub 2@ regardless of whether Cl@sub 2@ or HBr was used, and this resulted in a higher etch selectivity of Si to the underlying dielectric. As a result, a longer trimming time was allowed for HfO@sub 2@ than SiO@sub 2@. It was interesting to find out that an etching profile after the trimming step could be more anisotropic than that before the trimming step. Further studies are in progress to obtain 65nm trimmed gate structures from 130nm patterns using the 193nm photolithography technology.