AVS 50th International Symposium
    Plasma Science and Technology Monday Sessions
       Session PS-MoM

Paper PS-MoM6
Pattern Deformations during Resist Trimming Process and its Suppression by He-diluted O@sub 2@/SO@sub 2@ Chemistry

Monday, November 3, 2003, 10:00 am, Room 315

Session: Critical Dimension Etching
Presenter: H. Morioka, Fujitsu Limited, Japan
Authors: H. Morioka, Fujitsu Limited, Japan
M. Tajima, Fujitsu Limited, Japan
M. Terahara, Fujitsu Limited, Japan
M. Nakaishi, Fujitsu Limited, Japan
I. Hanyu, Fujitsu Limited, Japan
Correspondent: Click to Email
In addition to CD control, accuracy of pattern transcription in resist trimming and gate etching process, what is called pattern fidelity, has become more important with scaling of ULSI devices. Various pattern deformations during resist trimming, such as line-end shortening, often become serious obstacles to high-density device integration because they narrow the alignment margin and prevent the scaling of design rule. We measured line width reduction (amount of trimming) and the line-end shortening during trimming and gate etching process. Experiments were performed on an ICP etcher. O@sub 2@-base chemistry was used to "trim" resist patterns. The gate stack consisted of 1nm gate oxide, 100nm Poly-Si, and 30nm SiO@sub 2@, which was coated by organic BARC and patterned by ArF lithography. We found that the line-end shortening was larger than the line width reduction, and this disparity increased with increasing trimming time, which was accompanied by pattern deformations in specific patterns, such as L-shape corner. This pattern dependent resist erosion can be related to excessive etchant flux in the convex area. In order to suppress these disparity and pattern deformation, we investigated He/O@sub 2@/SO@sub 2@ chemistry, in which SO@sub 2@ was a source of lateral etching inhibitor that is mild to ArF resist, and oxygen was main etchant of trimming. He-dilution was used to control the trimming rate and suppress condensation of sulfur compounds. Optimizing etchant/inhibitor ratio by means of O@sub 2@/SO@sub 2@ ratio, we have succeeded in reducing line-end shortening and suppressing pattern deformations for trimming of sub-100nm resist patterns. In optimized conditions, trimming amount was almost the same as line-end shortening, and proximity effect (dense-iso differnce) of trimming was smaller than 5nm. Therefore we have fabricated 25nm gate poly-Si patterns by He/O@sub 2@/SO@sub 2@ trimming (from 80nm to 25nm) and conventional poly-Si gate etching process.