Semiconductor process control has advanced to address manufacturing needs -- primarily wafer to wafer uniformity of device and interconnect structures -- using improved metrology, real-time, and run-by-run control techniques. Here, the need for improved spatial uniformity is discussed, and the challenges for advanced process control in achieving these needs outlined. First, the impact of variation on integrated circuits of wafer to wafer, within wafer, and within die variation is considered, highlighting that yield and performance can depend at least as strongly on spatial uniformity as on wafer to wafer uniformity. Within die uniformity in particular pose difficult challenges; examples include uniformity in interconnect geometry (e.g. pattern dependent CMP and plating effects such as copper dishing and erosion), as well as device geometry and electrical properties (e.g. channel length variation due to lithography and plasma etch pattern dependencies). Finally, the resulting needs and challenges for process control are discussed: metrology must evolve to enable observation of within die variations, models are needed to relate control parameters to within die as well as across wafer results, and algorithms are needed that can address both spatial and temporal variation objectives.