AVS 50th International Symposium
    Manufacturing Science and Technology Tuesday Sessions
       Session MS-TuM

Invited Paper MS-TuM1
Challenges and Advances in Packaging Technology Development for IC Processing

Tuesday, November 4, 2003, 8:20 am, Room 309

Session: Packaging and Role of Interface Engineering in IC Processing
Presenter: H. Hosack, Semiconductor Research Corporation
Correspondent: Click to Email
Traditionally packaging provides isolation of the chip from the environment and a space transformation from the chip bond pads to leads compatible with connections to the outside world. With the recent increases in frequency and power dissipation in high performance microprocessors, and the advent of portable electronics, the requirements for electronic packaging are rapidly expanding not only to continuing increases in performance, but also to radically different functionality in areas such as photonics, RF, and MEMS. These new needs require complete re-thinking of packaging with the view that the die-package is a sub-system in itself, and the need is to produce this complete sub-system with optimized total performance at a minimum cost. The areas of critical importance in this sub-system view will be those areas that address the interface between the die back-end and the package. By eliminating unduly specialized work on either the chip or package in isolation, redundant effort can be minimized and device performance can be optimized. The challenges inherent in optimizing the chip-package interface include the spectrum of electrical issues, thermo-mechanical issues, and metrology. These issues are being addressed by package-chip interface solutions that not only optimize the sub-system in its present configuration but also by novel schemes that employ new materials, new signaling mediums, and reallocation of interface functions between the package and the chip. These new approaches include novel schemes such as incorporating portions of the traditionally on-chip metallization as a part of the package, non-contact chip-to-package signaling, and 3D packaging. This discussion describes the critical issues that must be addressed in this new view of package functions, as well as the status of some of the unique solutions that are being researched to provide the optimized chip-package sub-system.