Moore’s Law and the scaling principle have guided IC technology and products development in the past 3.5 decades, which has led us to sub 100nm era today. At the end of each decade IC technology community anticipated some sort of slowing down in the pace of geometry shrink, i.e.; in late 70’s it was 1um as the limit of practical scaling, and in late 80’s it became 0.1um as the ultimate limit. Now we are discussing 10-20nm as the ultimate limit. In the past cases, a set of technology break through allowed us further scaling, such as stepper technology and later excimer laser technology coupled with rapid thermal processing. At the same time we did not have physics driven limits in small geometry devices in the past, but now it seems there will be fundamental changes in transport phenomena in MOS transistors as geometry shrinks. The question today should be, "Do we have another break through which may bring us to sub-20nm in terms of performance, power consumption, cost and manufacturability?" If the answer is "no", we need to look into other options to partially, if not fully, replace scaled CMOS approach. This talk will cover the trends of CMOS scaling in the past, today and tomorrow, and discuss technical bottle neck and challenges mainly from device physics and technology point of view, followed by looking into several opportunities of nanoelectronic devices such as nanowires, nanotubes from device physics integration point of view.