AVS 50th International Symposium
    Manufacturing Science and Technology Monday Sessions
       Session MS-MoM

Paper MS-MoM5
Thermal Characterization of Stacked 3D System-in-Package

Monday, November 3, 2003, 9:40 am, Room 309

Session: Process and Equipment Integration and Development
Presenter: E.O. Ristolainen, Tampere University of Technology, Finland
Authors: J. Valtanen, Tampere University of Technology, Finland
J. Miettinen, Tampere University of Technology, Finland
E.O. Ristolainen, Tampere University of Technology, Finland
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Electronics development has been driven mainly by IC technology progress. Cell and line width have been continuously shrunk proving development trend called Moore's law. This has created increasing pressure to the first level interconnection. In future, traditional 2-dimensional (2D) packaging will limit product miniaturization. Therefore, components must be also joined to third dimension. A solution to this problem is a stacked System-in-Package (SiP). With this technology, great improvements over 2D packaging are achieved, such as greater packaging density, smaller size, and shorter interconnection length. The next evolution step comes in through following ways: to grind extra sand away from active ICs, to use flexible substrates and interposers. However, this technology has some problems that must be solved. For higher density of 3D package, increased power density brings new challenges to heat management. In this work, a stacked SiP structure has been studied. The package consists of three layers. In every layer, a silicon die of 3.7 mm x 8.3 mm has been joined with flip chip method onto an aramid-epoxy interposer of 6 mm x 10 mm. The silicon chips has been thinned down to 90 µm and the thickness of the interposer is 150 µm. The interposers are joined together using solder covered polymer spheres with diameter of 250 µm. So, the dimensions of whole package are 0.9 mm x 6 mm x 10 mm resulting in the total silicon efficiency of 150 %. Transient thermal responses have been measured by experiments and they are compared with simulations calculated with the FEM program Ansys. A constant heat power has been added to one chip at a time and temperature response has been measured in every chip. In this study, thermal responses, maximum temperatures, and chip-to-chip thermal interactions are achieved. In addition, differences between boundary conditions are discussed and certain design rules for chip placement are given.