AVS 50th International Symposium
    High-k Gate Dielectrics and Devices Topical Conference Tuesday Sessions
       Session DI-TuP

Paper DI-TuP2
Effects of Annealing Temperature on the Characteristics of HfO@sub 2@/HfSi@sub x@O@sub y@ High-k Gate Oxides

Tuesday, November 4, 2003, 5:30 pm, Room Hall A-C

Session: Poster Session
Presenter: H.-D. Kim, Sungkyunkwan University, Korea
Authors: H.-D. Kim, Sungkyunkwan University, Korea
Y. Roh, Sungkyunkwan University, Korea
D. Jung, Sungkyunkwan University, Korea
N.-E. Lee, Sungkyunkwan University, Korea
Correspondent: Click to Email
Several candidates for the future high-k gate oxides have been extensively studied by many research groups to overcome the problems such as large leakage current caused by the direct tunneling through extremely thin SiO@sub 2@. Recently, we reported that simple oxidation of sputtered Hf films on Si produces HfO@sub 2@/HfSi@sub x@O@sub y@ high-k oxides with excellent properties. We argued that the effective k of HfO@sub 2@/HfSi@sub x@O@sub y@ film may be controlled by changing the thickness ratio between HfO@sub 2@ and HfSi@sub x@O@sub y@. In this work, we further investigated the characteristics of HfO@sub 2@/HfSi@sub x@O@sub y@ high-k gate oxides to clarify the roles of annealing process. The 1.5 nm Hf film was directly deposited on Si substrate by sputtering at plasma power of 50 W for 4 min. Oxidation was performed at 500 °C for 60 min, followed by annealing at 500-900 °C in furnace under N@sub 2@ ambient. Pd gate metal was thermally evaporated on the HfO@sub 2@ film. Using the physical and electrical measurement techniques, we confirmed that the oxidation of the thin Hf films on Si results in the HfO@sub 2@/HfSi@sub x@O@sub y@ stack layer with the excellent electrical properties; negligible hysteresis, excellent EOT value (1.2 nm) and low leakage current (~2 X 10@super -3@ A/cm@super 2@ at 1.5 V after compensating V@sub fb@). Furthermore, we found that the level of leakage current decreases as annealing temperature increases. However, over 500 °C, annealing deteriorates the EOT value; e.g., 1.2 and 1.7 nm EOT values were obtained from 500 and 900 °C samples, respectively. We speculate that both thickness increase of HfO@sub 2@/HfSi@sub x@O@sub y@ films and the formation of additional SiO@sub 2@ layer between HfSi@sub x@O@sub y@ and Si cause these phenomena. We therefore suggest that annealing temperature must be carefully controlled to maintain the excellent characteristics of HfO@sub 2@/HfSi@sub x@O@sub y@ high-k gate oxides.