AVS 50th International Symposium
    High-k Gate Dielectrics and Devices Topical Conference Tuesday Sessions
       Session DI-TuM

Invited Paper DI-TuM1
Effects of Transistor Fabrication Process Conditions on Electrical Characteristics of High-k Gate Dielectrics

Tuesday, November 4, 2003, 8:20 am, Room 317

Session: High-k Dielectric Growth and Processing
Presenter: G. Bersuker, International Sematech
Authors: G. Bersuker, International Sematech
P. Zeitzoff, International Sematech
G.A. Brown, International Sematech
J. Gutt, International Sematech
N. Moumen, International Sematech
J. Peterson, International Sematech
J. Barnett, International Sematech
B.H. Lee, International Sematech
C.H. Lee, International Sematech
S. Gopalan, International Sematech
N. Chaudhary, International Sematech
Y. Kim, International Sematech
C. Young, International Sematech
P.S. Lysaght, International Sematech
H.-J. Li, International Sematech
M. Gardner, International Sematech
R.W. Murto, International Sematech
H.R. Huff, International Sematech
Correspondent: Click to Email
Comprehensive evaluation of high-k materials for gate dielectric applications requires fabrication of transistor test structures. The complex fabrication process includes several operations employing highly reactive ions, which may potentially affect electrical performance of the high-k materials. It is, therefore, critical from a materials evaluation standpoint to separate intrinsic properties of high-k dielectrics from process-related effects. The latter is the focus of this investigation. In particular, we concentrate on the charging problem associated with high-k materials, which appears to be one of the major factors affecting threshold voltage and mobility in high-k gate dielectric transistors. Our results demonstrate high sensitivity of the high-k films to the transistor fabrication process conditions. It is shown that electrical properties of gate stacks fabricated with a variety of combinations of ALD and MOCVD Hf-based dielectric compositions can be greatly affected by process-induced charges (PIC). PIC caused by negatively charged ions and/or electron trap inducing species may accumulate in the area of the high-k film exposed to various plasma operations during post gate definition processing (such as poly etch, ash/clean and spacer deposition). These contaminants may diffuse under the gate during subsequent high temperature processing and adversely affect device performance. Significant dependence of the electrical characteristics on the process scheme employed for the transistor fabrication complicates the evaluation of the intrinsic properties of the high-k gate dielectrics.