AVS 50th International Symposium
    High-k Gate Dielectrics and Devices Topical Conference Tuesday Sessions
       Session DI-TuA

Paper DI-TuA9
In-situ and Ex-situ Characterization of Barium Strontium Titanate Thin Films on Thermal SiO@sub 2@/Si Substrates

Tuesday, November 4, 2003, 4:40 pm, Room 317

Session: High-k Dielectric Characterization
Presenter: N.A. Suvorova, University of North Carolina, Chapel Hill
Authors: N.A. Suvorova, University of North Carolina, Chapel Hill
C.M. Lopez, University of North Carolina, Chapel Hill
A.A. Suvorova, University of Western Australia
M. Saunders, University of Western Australia
E.A. Irene, University of North Carolina, Chapel Hill
Correspondent: Click to Email
Alternative materials with high dielectric constant (k) are in demand for replacement of SiO2 in MOSFET devices. Barium strontium titanate (BST) is one of possible candidate for DRAM applications. The most important requirement for the incorporation of an alternative gate dielectric is to maintain a high quality interface with Si comparable to that of SiO2 /Si. Similar to other high k materials for BST this is a major problem due to interface reaction with Si. One potential solution is the use of a thermal SiO2 ultra thin underlayer, which helps to minimize the reaction between high k dielectric and Si as well as maintain the high interface quality. However this solution degrades the k values of the two film gate stack. The present study is aimed toward optimizing the SiO2 underlayer thickness in order to maintain the interface quality yet minimize the effect on k. The results from this optimization study are presented with emphasis on the key process parameters that improve the dielectric film stack. For in-situ growth characterization of BST film grown on thermally oxidized Si substrates spectroscopic ellipsometry has been used. Studies of material properties have been complemented with analytical electron microscopy. Electrical characterization has been employed for ex-situ studies of Pt/BST/SiO2/Si structures. From conductance-voltage analysis, the interface trap density Dit was observed to significantly decrease for the capacitors grown on oxidized Si substrates and annealed in forming gas.