The rapid pace of scaling CMOS technology has led to considerable attention in the area of high-k gate dielectrics. Since SiO@sub 2@ gate dielectrics are expected to have unacceptably high leakage current for most applications, high-k materials are of interest for producing lower leakage currents while maintaining similar device performance to SiO@sub 2@. Various high-k materials have been studied for this purpose recently, but it is clear that many important characteristics, which are already well known for SiO@sub 2@, have yet to be understood for any high-k material. To date, most high-k materials systems have exhibited the expected gate leakage reduction compared to SiO@sub 2@ of the same equivalent oxide thickness (EOT), but significant issues remain with respect to mobility degradation and threshold voltage shifts. Progress toward understanding these issues has been made over the past few years, yet controlling regions at both the channel and gate Si interfaces is still of critical importance to the success of any high-k material. Both physical and electrical analysis will be presented to highlight the key fundamental properties of high-k gate dielectrics, and how processing optimization has improved film quality. Characterization techniques such as electron energy loss spectroscopy (EELS) in scanning transmission electron microscopy (STEM), medium energy ion scattering (MEIS), X-ray Photoelectron Spectroscopy (XPS), Fourier transform infrared spectroscopy (FTIR) as well as electrical device properties will be presented.