AVS 50th International Symposium
    High-k Gate Dielectrics and Devices Topical Conference Monday Sessions
       Session DI-MoA

Paper DI-MoA5
Hafnium Silicate High-K Dielectric Etch with High Selectivity to Si at Low Wafer Temperatures

Monday, November 3, 2003, 3:20 pm, Room 317

Session: High-k Dielectric Stability
Presenter: C.B. Labelle, Advanced Micro Devices
Authors: S. Ramalingam, Lam Research Corporation
C.B. Labelle, Advanced Micro Devices
S.D. Lee, Lam Research Corporation
G.P. Kota, Lam Research Corporation
C. Lee, Lam Research Corporation
V. Vahedi, Lam Research Corporation
Correspondent: Click to Email
Advanced microprocessors require the use of increasingly thin gate oxide materials to achieve the highest performance. To date, these materials have consisted primarily of SiO2 and nitridized SiO2, but the leakage current behavior of these materials becomes undesirable as they are successively thinned (=12Å). A potential solution to this problem is replacement of SiO2 by an insulator with a higher dielectric constant (high k). Keeping with current integration schemes, gate etching would then require etching through the polysilicon and high-k materials, stopping on the underlying silicon. However, high-k materials have proven very challenging to etch, specifically due to the low volatility of etch products, which typically require an aggressive approach to the etch, most notably including high temperatures. Key etch issues include selectivity to polysilicon/bulk silicon and masking material, redeposition of high k materials on the poly gate sidewalls, and altering of the poly gate profile and/or CD. A Lam 2300 SeriesTM silicon etch reactor has been used to etch photoresist-masked polysilicon gate wafers with HfSiOx gate dielectric. A BCl3-based process has been developed that provides excellent selectivity to polysilicon, no high k redeposition, and <10Å silicon recess. Selectivity to Si is attained at low ion energy and through passivation of the surface by formation of Si-B bonds. A key advantage of this process over those currently in practice is that wafer temperatures higher than those in typical gate etch processes are not necessary. Key etch results will be presented, including analysis of the impact of a boron-based etch process on gate doping.