AVS 49th International Symposium
    Plasma Science Tuesday Sessions
       Session PS-TuP

Paper PS-TuP29
Process-Induced Damage by the Low Angle Forward Reflected Neutral Beam Etching

Tuesday, November 5, 2002, 5:30 pm, Room Exhibit Hall B2

Session: Plasma Applications
Presenter: D.H. Lee, Sungkyunkwan University, Korea
Authors: D.H. Lee, Sungkyunkwan University, Korea
M.J. Chung, Sungkyunkwan University, Korea
H.K. Hwang, Sungkyunkwan University, Korea
G.Y. Yeom, Sungkyunkwan University, Korea
Correspondent: Click to Email
Plasma etching is one of the key technologies in the fabrication of deep submicron silicon based integrated circuits. However, plasma etching has a serious disadvantage due to the energetic charged particles such as positive ions and photons generated in the plasma which causes radiation damage causing physical defect, increased gate oxide breakdown, charging, etc. To avoid these charge-related and physical impact-related damages, several low-damage processes have been proposed. One possible alternative to avoid these problems is a low energy neutral beam etching. In the previous study, a neutral beam was formed using a low angle forward reflected neutral beam technique as a possible anisotropic etching technique without charging and its degree of neutralization and etch characteristics were investigated. When the ion beam was reflected at a reflector at the angles lower than 15 degrees, most of the ions reflected were neutralized and the lower reflector angle showed the higher degree of neutralization. In this study, process-induced damages during the etching of SiO@sub 2@ were investigated in addition to the etch rates and the etch properties of SiO@sub 2@ for fluorine-based gases using the low angle forward reflected neutral beam etching system. Surface contamination was performed by X-ray photoelectron spectroscopy (XPS) and Auger electron spectroscopy (AES). Also, possible neutral beam induced charge damage was examined through electrical characteristics such as C-V, I-V, and breakdown voltage of the gate oxide and the Si-SiO@sub 2@ interface after the etching.