Recent advances in ultra large-scale integration (ULSI) have typically depended on reductions in etched feature size. This has motivated efforts to find etch processes that will precisely etch increasingly smaller features while retaining the ability to etch larger features. As feature sizes push below 0.25 µm, reactive ion etch (RIE) lag control becomes increasingly important. Knowing how RIE lag scales with feature size for a given process aids in determining if that process must be discarded and a new one developed. In those situations where a process cannot be discarded, an understanding of RIE lag scaling aids in predicting fabrication difficulties for a given device design. Using a minimal set of initial assumptions, it is shown that a relationship can be derived which relates etch rate to the time development of the feature aspect ratio. It is then shown that this relationship can be used to derive an expression for the etch depth as a function of time and feature size. The assumptions made are justified by phenomenological observation rather than by an assumed mechanism. This approach enhances the generality of the results obtained, thus making them useful for a variety of practical etch engineering applications.