AVS 49th International Symposium
    Dielectrics Thursday Sessions
       Session DI+EL-ThM

Paper DI+EL-ThM9
Hafnium Silicate and Nitrided Hafnium Silicate as Gate Dielectric Candidates for SiGe-based CMOS Technology

Thursday, November 7, 2002, 11:00 am, Room C-107

Session: Issues for Gate Dielectrics
Presenter: S. Addepalli, University of North Texas
Authors: S. Addepalli, University of North Texas
P. Sivasubramani, University of North Texas
H. Zhang, University of North Texas
M. El-Bouanani, University of North Texas
M.J. Kim, University of North Texas
B.E. Gnade, University of North Texas
R.M. Wallace, University of North Texas
Correspondent: Click to Email
Strained epitaxial Si@sub x@Ge@sub 1-x@ layers on Si have attracted considerable technological interest due to the enhancement in hole mobility, as well as ease of integration with existing Si CMOS technology. One of the major drawbacks, however, is the inability to produce a high-quality gate oxide in direct contact with Si@sub x@Ge@sub 1-x@, while maintaining the integrity of the oxide-Si@sub x@Ge@sub 1-x@ interface. The introduction of a stable high-@kappa@ dielectric provides the prospect of simultaneously enhancing the capacitance of the gate stack and reducing leakage current for high performance SiGe devices. We have investigated hafnium silicate and nitrided hafnium silicate as viable candidates for SiGe-based CMOS technology. Hafnium silicide and nitrided hafnium silicide films were sputter deposited directly on Si@sub x@Ge@sub 1-x@. These films were subsequently converted to hafnium silicate and nitrided hafnium silicate respectively by employing a room temperature UV-ozone assisted oxidation approach in order to preserve the pseudomorphic nature of the Si@sub x@Ge@sub 1-x@ layers. The bonding and composition of these films were characterized by X-ray photoelectron spectroscopy (XPS), Fourier Transform Infrared Spectroscopy (FTIR), and Rutherford Backscattering Spectrometry (RBS). The deposition and post-deposition processing parameters were optimized using XPS, High-resolution transmission electron microscopy (HRTEM), and FTIR. The electrical performance of the films was evaluated from capacitance-voltage (C-V) and current-voltage (I-V) measurements. The effects of various post-deposition annealing treatments on the electrical performance of the films were also studied. This work is supported by DARPA through SPAWAR Grant No. N66001-00-1-8928, and the Texas Advanced Technology Program.