AVS 49th International Symposium
    Dielectrics Thursday Sessions
       Session DI+EL-ThM

Paper DI+EL-ThM4
The Effect of N@sub 2@ Annealing on Al@sub x@Zr@sub y@O@sub z@ Oxide

Thursday, November 7, 2002, 9:20 am, Room C-107

Session: Issues for Gate Dielectrics
Presenter: J. Pétry, IMEC, Belgium
Authors: J. Pétry, IMEC, Belgium
O. Richard, IMEC, Belgium
W. Vandervorst, IMEC, Belgium
T. Conard, IMEC, Belgium
J. Chen, International Sematech c/o IMEC, Belgium
V. Cosnier, International Sematech c/o IMEC, Belgium
Correspondent: Click to Email
In the path to the introduction of high-k dielectric into IC components, a large number of challenges have to be solved. One of these concerns the stability of high-k oxides to high temperature annealing. Indeed annealing will most likely be necessary to improve the electrical characteristics of the high-k layer itself and the high-k stack will be submitted to annealing in further processing. In this study, we investigated the effect of annealing of ALCVD AlZrO layers in N@sub 2@ from 700 to 900C by XPS, TOFSIMS, TEM and FTIR. The effect of the Si surface preparation (HF-last, 0.5 nm RTO, Al@sub 2@O@sub 3@) on the modification of high-k oxide and interfacial layer upon annealing was also analyzed. We first studied the compositional changes of the mixed oxide upon annealing. For all temperature and surface preparation considered, we observed a segregation of the mixed oxide with the Al oxide at the surface. We also observed an increase of the Si concentration in the high-k film itself, with a diffusion profile towards the surface of the film. On the other hand, the modification of the interfacial layer is strongly dependent on the system considered. In the case of mixed oxide grown on 0.5 nm RTO, no changes are observed between the as-deposited layer and the layer annealed at 700C. At 800C, radical change appears: the initial RTO layer seems to be converted to a mixed layer composed of the initial SiO@sub 2@ and AlO coming from the mixed oxide, without forming an Al-silicate layer. This remains for annealing at 900C. When grown on 1.5 nm Al@sub 2@O@sub 3@ on 0.5 nm RTO, the only difference from the previous system is the observation of an Al-silicate fraction in the interfacial layer for the as-deposited and 700C annealed samples, which disappears at higher temperatures. Finally, when grown on HF-dipped Si, we observe a slight increase of the interfacial thickness after annealing at 700C and no further changes for higher annealing temperature.