AVS 49th International Symposium
    Dielectrics Thursday Sessions
       Session DI+EL-ThA

Paper DI+EL-ThA1
Plasma Etch Processes for Ferroelectric Memory Integration

Thursday, November 7, 2002, 2:00 pm, Room C-107

Session: Processing and Properties of Dielectric Materials
Presenter: F.G. Celii, Texas Instruments
Authors: F.G. Celii, Texas Instruments
M. Thakre, Texas Instruments
S. Summerfelt, Texas Instruments
S. Aggarwal, Texas Instruments
J.S. Martin, Texas Instruments
K.R. Udayakumar, Texas Instruments
T.S. Moise, Texas Instruments
Correspondent: Click to Email
Embedded ferroelectric memory has the potential to enable increased functionality, reduced power, and potentially lower cost for portable electronics applications. In recent years, several companies have demonstrated lateral scaling of ferroelectric capacitors needed to realize high-density capacitor arrays consistent with low-cost requirements. In this paper, we summarize our current status towards integration of FeRAM capacitors into a CMOS flow, with emphasis on the etch processes. We review the various schemes for FeRAM integration and highlight our selected multi-height Via approach. In this approach, we define the Ir / PZT / Ir capacitors by a combination of hardmask and capacitor stack etches. Following encapsulation and interlevel dielectric deposition, the Via-0 pattern is applied and etched, utilizing a high-selectivity oxide etch to give the bi-level Via-0 etch profile. Electrical results from integrated and non-integrated capacitors will be presented.