IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Plasma Science Thursday Sessions
       Session PS-ThP

Paper PS-ThP6
Surface Analysis of a High Selective Polysilicon to Oxide Plasma Etching Process

Thursday, November 1, 2001, 5:30 pm, Room 134/135

Session: Plasma Etching Poster Session
Presenter: T. Tai, IBM, SRDC
Authors: T. Tai, IBM, SRDC
S. Molis, IBM, SRDC
W. Yan, IBM, SRDC
Correspondent: Click to Email

With continuing reduction of minimum feature size in semiconductor device fabrication, limited gate stack height becomes necessary to control the bitline?wordline capacitance, and to reduce bitline contact aspect ratio for better process performance. Tungsten, which has a lower sheet resistance and hence the capability to reduce gate stack height, has been selected to replace widely used tungsten silicide in the gate structure. However; because of the chemical nature of tungsten, tungsten to oxide RIE selectivity in the Fluorine etching enviroment is not adequate to prevent thin gate oxide (less than 40A) to be punched through. A polysilicon etch step with adequate selectivity to oxide has been developed to prevent gate oxide punchthrough. Xray Photoelectron spectroscopy and Time-of-Flight Secondary Ion mass spectrometry were applied to investigate the Poly and Oxides in a high-density plasma etching environments with HBr/Cl2/O2 chemistry. The results will lead to the undertanding of the RIE chemistry that provide the selectivity.