W/poly Si stack becomes potential candidate in giga bit DRAM gate structure due to its lower sheet resistance compared to WSi/poly Si stack. Emerging process issues in W gate module are high etch selectivity of W over Si@sub 3@N@sub 4@ mask and poly Si stack down for self aligned contact scheme. High temperature process was evaluated in W etching to achieve high etch selectivity based on Cl@sub 2@/O@sub 2@ gas chemistry in a dual frequency plasma reactor. Mask loss and W profile were found to be strong function of gas ratio, process pressure and ion energy. The presence of oxygen inhibited Si@sub 3@N@sub 4@ mask loss by oxidation while enhancing W etching at high process temperature (150°C). Two steps W etch was developed in order to reduce the recess of poly Si in W overetch step. Poly Si recess showed a different behavior with Cl@sub 2@/O@sub 2@/NF@sub 3@ based gas chemistry at the temperature raging from 100°C to 150°C. Recess was optimized at 120°C at the expense of mask loss and W profile. Conventional HBr based chemistry appeared to have inability to provide sidewall passivation in poly Si etching at high temperature. Gas chemistry for sidewall passivation and high selectivity over gate oxide at high temperature will be discussed.