IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Plasma Science Thursday Sessions
       Session PS-ThP

Paper PS-ThP18
Damage Free Gate Shrinkage Method Using Low Temperature Si@sub 3@N@sub 4@ Film Deposition and SF@sub 6@/O@sub 2@ Gas Mixture Etching

Thursday, November 1, 2001, 5:30 pm, Room 134/135

Session: Plasma Etching Poster Session
Presenter: C.R. LIM, LG-Elite (LG-Electronics Institute of Technology), South Korea
Authors: C.R. LIM, LG-Elite (LG-Electronics Institute of Technology), South Korea
J.H Shin, LG-Elite (LG-Electronics Institute of Technology), South Korea
Correspondent: Click to Email
Recently, the concern about sub micron gate length formation method for development of high performance FET is increasing. But, sub micron gate length could not be gotten using optical contact aligner or cheap stepper machine. And, in order to reduce resistance in FET gate electrode which had short gate length, we use normally T-shaped gate whose head was wide about 1 micrometer. In our lab, we tried to make FET whose gate length was shorter than the exposed gate length. After lithography of about 0.4 micrometer gate length using stepper, and we deposited silicon nitride film at low temperature to protect photo resist from deformation and at low work pressure to form conformal shape. Deposited silicon nitride film was etched using conventional RIE medium-pressure reactor and we tried to find proper etch condition from varied SF@sub 6@/O@sub 2@ gas ratio and could know proper etch condition of the ratio 3:7 at work pressure 100mTorr and RF power of 100watt. Doing so, we could get FET which has gate length of 0.1 micrometer and the deposition and etching condition harm no damage on wafer surface. In order to find low temperature silicon nitride film deposition condition and directional etching condition, we used SEM, optical emission spectroscopy and dielectric constant measurements.