IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Plasma Science Thursday Sessions
       Session PS-ThP

Paper PS-ThP16
Trench Etch Challenges in a Cu/Low-k Via-First Dual Damascene Scheme

Thursday, November 1, 2001, 5:30 pm, Room 134/135

Session: Plasma Etching Poster Session
Presenter: P. Jiang, Texas Instruments, Inc.
Authors: P. Jiang, Texas Instruments, Inc.
H. Hong, Texas Instruments, Inc.
Q. Hong, Texas Instruments, Inc.
K.J. Newton, Texas Instruments, Inc.
Correspondent: Click to Email
In a via-first copper dual damascene integration scheme, trench patterning is one of the most critical steps, for both lithography and etch. Due to via topography, resist thinning occurs in dense via region during trench pattern, resulting in potential resist breakdown during trench etch. To prevent trench bridging or metal shorting, it becomes necessary to keep good trench etch profile and high resist selectivity. However, another key issue for trench etch is oxide ridge formation around vias which can disrupt metallic barrier and copper deposition resulting in degraded device reliability. In achieving good trench profile and high resist selectivity, oxide ridges often become severe. Therefore, it is very challenging to control profile, resist selectivity and oxide ridge formation simultaneously. In this paper, we will discuss the options and results that meet the special requirements for Cu/low-k dual damascene trench etch. The low-k dielectric film used in this work was an organosilicate glass (OSG). The effect of etch process parameters on trench profile, resist selectivity and ridge formation will be discussed, along with the resist effect on resist etch selectivity. Electrical results showing significant yield improvement with the optimal etch process will also be reported.