IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Plasma Science Thursday Sessions
       Session PS+MS-ThM

Paper PS+MS-ThM6
Manufacturing Viability of the "Notched Gate" Process for sub 0.1µm Technologies

Thursday, November 1, 2001, 10:00 am, Room 104

Session: Conductor Etch and Damage
Presenter: J. Foucher, CNRS/LTM, France
Authors: J. Foucher, CNRS/LTM, France
L. Vallier, CNRS/LTM, France
G. Cunge, CNRS/LTM, France
O. Joubert, CNRS/LTM, France
T. Lill, Applied Materials
Correspondent: Click to Email
The development of new integrated circuit generations, at a unique rate in the semiconductor history, imposes the development of new technologies. Recently, Integrated Circuit manufacturers have evaluated new strategies to make gate transistors smaller than the resolution allowed by the lithographic tool available for manufacturing. One of them is to decrease the resist feature dimension before gate etching (resist trimming), the other approach is to design a "notched gate" etch process with a controlled etch rate of silicon in the lateral direction (the bottom of the gate is smaller than its top). We first describe in details the main differences between a notched gate process and a standard gate etch process and introduce the notion of passivation layer engineering. We demonstrate that when the process is accurately tuned, gate dimension of 10 nm can be obtained on a 200 mm diameter wafer. We mainly concentrate on several aspects of the process which determine its industrial viability: - What are the plasma operating conditions and chemistry required to stabilize a "notched gate" process or in other words what are the impact of the wall conditions on notch reproducibility ? - Can we solve the CD control issues of the notched gate process ? We will present experimental data demonstrating clearly that the notch depth rate is strongly dependent on the gate environment. In other words, the lateral etch rate which controls the notch depth is aspect ratio dependent and impacted by the plasma non-uniformity. In conclusion, we clearly demonstrate the strong limitations of the notched gate process for manufacturing.