IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Plasma Science Thursday Sessions
       Session PS+MS-ThM

Invited Paper PS+MS-ThM3
Silicon Gate Etching: Potential Strategies for Future CMOS Devices

Thursday, November 1, 2001, 9:00 am, Room 104

Session: Conductor Etch and Damage
Presenter: G. Cunge, CNRS/LTM, France
Authors: G. Cunge, CNRS/LTM, France
L. Vallier, CNRS/LTM, France
O. Joubert, CNRS/LTM, France
J. Foucher, CNRS/LTM, France
X. Detter, CNRS/LTM, France
Correspondent: Click to Email
In less than ten years CMOS devices will operate in the sub-50 nm gate length regime. The fabrication of the gate will be the key issue of the device fabrication process since the variation in gate dimension must not exceed the nominal CD targeted by few nm. In this work, some of the most promising gate strategies are investigated 1) resist mask on SiON antireflective layers versus hard mask approaches 2) standard HBr/Cl@sub2@/O@sub2@ chemistries versus CF@sub4@ (or NF@sub3@) added chemistries. The origin of CD deviation are investigated for each single step of the different strategies: correlations between chemistry and plasma operating conditions analysed by mass spectrometry, passivation layer formation on the feature sidewalls analysed by XPS and CD deviation will be established. Our preliminary experiments show that the passivation layers formed on the mask sidewalls induce very severe CD gain during standard gate etch steps. The objective is first to minimize the CD deviation induced by each individual step of the process (by decreasing the passivation layer thickness). Ultimately, the process has to be tuned so that the CD loss or gain of each individual step compensate each other to maintain the CD in the targeted window. In final, by comparing the impact of mask materials as well as the impact of chemistries (standard or clean) on CD control, we may give some interesting conclusions on the most promising strategy. In parallel to this study, we evaluate the current strategies used to obtain gates smaller than the dimension printed by the lithography (resist trimming or "notched gate approach") and try to draw some clear conclusions on the best approach for manufacturing.