IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Dielectrics Monday Sessions
       Session DI1-MoP

Paper DI1-MoP4
Investigation of Tungsten Silicide Gate for the Integration with High-k Hafnium Oxide (HfO@sub 2@) in Metal-Oxide-Semiconductor Devices

Monday, October 29, 2001, 5:30 pm, Room 134/135

Session: High K Dielectrics Poster Session
Presenter: K. Roh, Sungkyunkwan University, Korea
Authors: K. Roh, Sungkyunkwan University, Korea
S. Yang, Sungkyunkwan University, Korea
H. Kang, Sungkyunkwan University, Korea
Y. Roh, Sungkyunkwan University, Korea
G. Bae, Sungkyunkwan University, Korea
D. Jung, Sungkyunkwan University, Korea
N.-E. Lee, Sungkyunkwan University, Korea
C.-W. Yang, Sungkyunkwan University, Korea
Correspondent: Click to Email
Sub-0.1 µm MOSFETs face a scaling limit when a SiO@sub 2@ gate dielectric is used due to high direct tunneling leakage current. Recently, many high-k gate dielectrics such as Al@sub 2@O@sub 3@, Y@sub 2@O@sub 3@, ZrO@sub 2@, HfO@sub 2@ and their stacks have been studied extensively to replace thermal SiO@sub 2@. Among those dielectrics, Hafnium oxide and their silicates have been suggested as a strong candidate for the alternate gate oxides. In this work, we report the structural and electrical properties of HfO@sub 2@ films with tungsten silicide (WSi@sub 2@) as a metal gate. The samples were fabricated on 4-in n- and p-type (100) wafers with 4~7 @ohm@cm resistivity. Hf films were deposited using rf reactive magnetron sputtering method from 99.5 % Hf target on the Si wafers, and were thermally oxidized in furnace at 500 °C. Annealing of the formed HfO@sub 2@ in furnace at 500 °C was then followed. During sputtering, the gas pressure and rf power were 10 mTorr and 50 W, respectively. Tungsten silicide films for gate electrode were deposited directly on the HfO@sub 2@ films in a cold-wall low pressure chemical vapor deposition system with the thickness of 500 ~ 1500 Å. For electrical characterization, the WSi@sub 2@/HfO@sub 2@/Si MOS capacitors were. Additional annealing was carried out at various conditions to minimize the resistance of WSi@sub 2@ and etching damage. The hysteresis of the WSi@sub 2@/HfO@sub 2@/Si MOS capacitors before and after annealing was negligible (<10 mV); it was independent on frequencies from 10 kHz to 1 MHz and on bias ramp rates from 10 mV to 1 V. Gate depletion effect was not also observed. After furnace annealing of the WSi@sub 2@/HfO@sub 2@/Si MOS capacitors at 500 °C, EOT (equivalent oxide thickness) was reduced from 26 to 22 Å. In addition, the leakage current was 1x10@super -5@ A at 1 V after annealing, which is reduced by approximately one order as compared to that measured before annealing.