IUVSTA 15th International Vacuum Congress (IVC-15), AVS 48th International Symposium (AVS-48), 11th International Conference on Solid Surfaces (ICSS-11)
    Dielectrics Monday Sessions
       Session DI-MoA

Invited Paper DI-MoA1
Epitaxial High-K Gate Oxides on Silicon: Impact on Future CMOS

Monday, October 29, 2001, 2:00 pm, Room 130

Session: High K Dielectrics I
Presenter: Z. Yu, Motorola Labs
Authors: Z. Yu, Motorola Labs
R. Droopad, Motorola Labs
J. Ramdani, Motorola Labs
J. Curless, Motorola Labs
C. Overgaard, Motorola Labs
J. Finder, Motorola Labs
K. Eisenbeiser, Motorola Labs
J. Wang, Motorola Labs
W. Ooms, Motorola Labs
Y. Liang, Pacific Northwest National Laboratory
S.A. Chambers, Pacific Northwest National Laboratory
Correspondent: Click to Email
One of the main problems facing the semiconductor industry is the scaling of the gate dielectric of silicon CMOS devices. Currently, SiO@sub 2@ gate oxide is being used, but it suffers from tunneling leakage current and reliability problems at thickness below 2 nm. Alternative high-k materials to replace SiO@sub 2@ need to be developed as soon as possible. Single crystal oxides such as SrTiO@sub 3@ (STO) with a simple structure and a much higher k are ideal candidates for future CMOS gate dielectrics. A physically thick high-k layer can behave electrically like a thin one, thereby eliminating the tunneling leakage problems experienced with <2 nm SiO@sub 2@. These oxides also exhibit ferroelectric behavior and their use as the gate dielectric on Si can be exploited in the realization of a single transistor memory element. In this presentation, we will review the atomic simulation, MBE growth, structural, electrical and interface properties of high quality single crystal STO layers on Si with low leakage current density and effective oxide thickness (EOT) < 1 nm. The STO layers are characterized using RHEED, SE, XRD, AFM, TEM and XPS. Atomic simulations have been extensively carried out to predict the reliability of the structure of the epi-oxide/Si interface. The oxide films on Si(001) are (001) orientated as determined by XRD and pole figure analysis confirms that the perovskite oxide lattice is rotated 45° with respect to the Si lattice. AFM measurements shows rms roughness as low as 1.2 Å. Cross-sectional TEM shows smooth interfaces and dislocation free STO films. XPS has been used to determine the band offsets at the oxide/Si interface. Electrical measurements on MOS capacitors fabricated on wafer using platinum gate electrodes demonstrated leakage as low as 10@super -8@ A/cm@super 2@ with interface state densities in the low 10@super -11@ cm@super -2@eV@super -1@. Results on MOSFET devices fabricated using STO as the gate insulator will be presented.