AVS 47th International Symposium
    Semiconductors Wednesday Sessions
       Session SC+EL+SS-WeP

Paper SC+EL+SS-WeP3
Lowering of Processing Temperature due to a High Pressure Deuterium Anneal for Improved CMOS Hot Carrier Reliability

Wednesday, October 4, 2000, 11:00 am, Room Exhibit Hall C & D

Session: Poster Session
Presenter: J. Lee, University of Illinois, Urbana
Authors: J. Lee, University of Illinois, Urbana
K. Cheng, University of Illinois, Urbana
K. Hess, University of Illinois, Urbana
J.W. Lyding, University of Illinois, Urbana
Y.K. Kim, Samsung Electronics Co., Ltd.
Y.W. Kim, Samsung Electronics Co., Ltd.
K.P. Suh, Samsung Electronics Co., Ltd.
Correspondent: Click to Email
The deuterium (D) isotope effect has been found to be very effective in reducing hot carrier induced degradation in CMOS transistors of numerous technologies. The magnitude of lifetime improvement (10x to 100x) varies from one technology to the other, but it directly correlates with D incorporation at the gate SiO@sub 2@/Si interface. Secondary ion mass spectrometry (SIMS) depth profiling has been used to make this determination. We have recently implemented high pressure D annealing to enhance its incorporation at the interface. By increasing the D pressure, the concentration at the interface can be increased for a fixed annealing temperature. Consequently, lower temperatures and shorter anneal times can achieve equivalent transistor reliability. This promises to be a technologically significant result for future CMOS production which requires a much lower thermal budget process due to the introduction of advanced materials (e.g. low k dielectrics) and increased number of metal layers. This high pressure annealing technique has been applied to one of the most recent CMOS technologies from Samsung Electronics. For these short-channel (0.18 µm) and low operating voltage (1.5V) devices, the isotope effect is substantially enhanced (700x). Rather than being scaled away, deuterium reduction of hot electron damage appears more relevant in future generations of CMOS integrated circuits. In the current work, the annealing temperature has been lowered from 450@degree@C to 350@degree@C. Although the lifetime improvement is not as great, we do observe a significant lifetime improvement (300x) just from changes in pressure. More experiments are in progress to maximize the D incorporation at the low annealing temperature. In addition, SIMS depth profiles are being determined for devices that were sintered at different annealing conditions.