AVS 47th International Symposium
    Plasma Science and Technology Thursday Sessions
       Session PS2-ThA

Paper PS2-ThA10
Trench Etch Processes for Dual Damascene Patterning of Low-k Dielectrics

Thursday, October 5, 2000, 5:00 pm, Room 311

Session: Dielectrics I
Presenter: P. Jiang, Texas Instruments, Inc.
Authors: P. Jiang, Texas Instruments, Inc.
F.G. Celii, Texas Instruments, Inc.
W.W. Dostalik, Texas Instruments, Inc.
K.J. Newton, Texas Instruments, Inc.
H. Sakima, Tokyo Electron America
Correspondent: Click to Email
The use of dual damascene patterning for integration of Cu with low-k dielectric films has introduced new challenges for plasma etch processes. With a via-first dual damascene approach, an important issue for trench etch is defect formation (i.e., oxide ridges) around vias which can degrade device reliability. The use of low-k films as the dielectric material adds additional complexity and more limitation on the etch process parameters. This paper discusses the development of etch processes that meet the special requirements for Cu/low-k dual damascene trench etch. All experiments were conducted in a medium-density TEL Dipole Ring Magnetron (DRM) system. The dielectric film used here was an organosilicate glass (OSG). Using C@sub 4@F@sub 8@/N@sub 2@/Ar chemistry, a trade-off was observed between etch rate and oxide ridge formation. The N@sub 2@/Ar ratio was found to be the key parameter in controlling the severity of the oxide ridges, but eliminating the ridges using the N@sub 2@/Ar ratio resulted in a low OSG etch rate and poor throughput. However, we will discuss an alternative method which achieves high OSG etch rate while maintaining CD control and ridge-free conditions. The effect of various process parameters on the OSG etch rate and ridge formation will be detailed. A comparison of experimental results against numerical simulations of C@sub 4@F@sub 8@-based bulk plasmas with varying gas flow ratios will also be reported.