AVS 47th International Symposium
    Manufacturing Science and Technology Thursday Sessions
       Session MS-ThA

Paper MS-ThA9
Contamination Removal from Wafer with Deep Trenches

Thursday, October 5, 2000, 4:40 pm, Room 304

Session: Advanced Modeling for IC Manufacturing
Presenter: H. Lin, NSF and CAMP (New York Center for Advanced Materials Processing, at Clarkson University)
Authors: H. Lin, NSF and CAMP (New York Center for Advanced Materials Processing, at Clarkson University)
A.A. Busnaina, NSF and CAMP (New York Center for Advanced Materials Processing, at Clarkson University)
I.I. Suni, NSF and CAMP (New York Center for Advanced Materials Processing, at Clarkson University)
Correspondent: Click to Email
The International Technology Roadmap for Semiconductors shows the requirement for high aspect ratio (depth/width) trenches in DRAM trench capacitor technology. Cleaning high aspect ratio deep trenches is challenging because of the need to rinse or remove contaminants from the bottom of trench. In this work, based on the experimental and numerical study of blanket wafer cleaning, contamination removal from wafer with topography is studied using physical modeling. The rinsing flow and contaminant transport in the geometry are modeled by solving the governing momentum and mass conservation equations with associated boundary conditions. The rinsing of patterned wafer is accomplished using an oscillating flow past a series of high ratio rectangular trenches. The modeling results of flow past a series of trenches show a good agreement with the experimental results of Perkins. Oscillating flow rinse is found to be more efficient than steady flow rinse using the same average rinsing velocity. The effects of the aspect ratio, trenches size, and oscillating flow frequency on cleaning efficiency are presented.