AVS 47th International Symposium
    Manufacturing Science and Technology Thursday Sessions
       Session MS-ThA

Paper MS-ThA8
Etching of Silicon in HBr Plasmas for High Aspect Ratio Features

Thursday, October 5, 2000, 4:20 pm, Room 304

Session: Advanced Modeling for IC Manufacturing
Presenter: H.H. Hwang, ELORET Corp.
Authors: H.H. Hwang, ELORET Corp.
G.S. Mathad, Infineon Technologies, Inc.
R. Ranade, Infineon Technologies, Inc.
M. Meyyappan, NASA Ames Research Center
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Acquiring straight wall etching is a continuing goal in the semiconductor processing industry. Achieving a vertical wall with no bowing becomes extremely critical as dimensions decrease to less than 0.1 µm. Undercutting must be minimized in order to obtain closely spaced features of this size. Etching typically requires aspect ratios on the order of 20:1 (depth:width) and often higher than 50:1. At these small feature sizes and large aspect ratios, neutral shadowing becomes increasingly more important. Fewer neutral radicals which can passivate the substrate surface can enter the trench opening, which leads to a decreased etch rate and can limit the maximum obtainable aspect ratio (AR). In pure chlorine, for example, it is difficult to achieve ARs of more than 5:1. To date, however, most modeling efforts have not focused on the specific problems encountered in high aspect ratio etching. We will present results for etching silicon in HBr plasmas using a previously developed feature profile evolution simulation using a level set method (SPELS). We will compare calculated average etch rates, total etched depth, and RIE lag effects (etch rate dependence on feature size) in high aspect ratio trenches to experimental measurements. The measurements were made in a parallel plate, capacitively-coupled, magnetically enhanced reactor. We will also present comparisons in etch rates for different feature sizes (0.2 µm, 0.175 µm, and 0.15 µm). Comparisons of simulated etched profiles and experimentally obtained SEMS will also be presented.