AVS 47th International Symposium
    Manufacturing Science and Technology Monday Sessions
       Session MS-MoM

Paper MS-MoM3
Application of Scanning Capacitance Microscopy to the Characterization of Semiconductor Device Operation

Monday, October 2, 2000, 9:00 am, Room 304

Session: Metrology for IC Manufacturing
Presenter: C.Y. Nakakura, Sandia National Laboratories
Authors: C.Y. Nakakura, Sandia National Laboratories
D.L. Hetherington, Sandia National Laboratories
M.R. Shaneyfelt, Sandia National Laboratories
P.E. Dodd, Sandia National Laboratories
Correspondent: Click to Email
Scanning capacitance microscopy (SCM) has become increasingly used for the study of semiconductor doping due to its ability to measure two-dimensional free carrier profiles with nanometer-scale resolution. The bulk of recent SCM work has focussed on carrier profile measurements in cross-sectioned, metal-oxide-semiconductor field-effect transistors (MOSFETs); however, limitations in the hardware and sample structures have restricted most studies to non-functioning devices. To address this, we have modified a commercial SCM and fabricated specially designed test structures that provide independent electrical access to the device regions, enabling the use of SCM to study actively biased devices. By recording images while incrementally increasing the gate bias voltage, we were able to visualize devices switching between the off and on states. The evolution of the SCM images as a function of operating bias provides insight into changes in the channel region during MOS device operation and will be presented in movie form. Complications in image formation, which arise from biasing the device, will be discussed. @FootnoteText@ This work was performed at and supported by Sandia National Laboratories under DOE contract DE-AC04-94AL85000. Sandia National Laboratories is a multi-program laboratory operated by Sandia Corporation for the United States Department of Energy.