AVS 47th International Symposium
    Manufacturing Science and Technology Monday Sessions
       Session MS-MoA

Invited Paper MS-MoA9
Process Integration Challenges in a Copper/Low-K World

Monday, October 2, 2000, 4:40 pm, Room 304

Session: Challenges in Semiconductor Manufacturing for the First Decade of the 21st Century
Presenter: R.A. Powell, Novellus Systems
Correspondent: Click to Email
It is generally agreed that the wiring of GigaHertz-class ICs will be a multilevel interconnect stack of Cu lines electrically insulated from each other by low-k interlevel dielectrics and assembled using a Damascene process flow. Significant progress has already been made on unit processes needed for 0.10-0.13 µm technology, including deposition of conformal barrier/seed layers by ionized PVD or CVD, bottom-up filling of vias and trenches using additive-enhanced Cu electroplating, and deposition and patterning of CVD and spin-on dielectrics having dielectric constant in the range 2 < k < 3. On the other hand, integrating these unit processes together without losing the intrinsic material benefits of Cu and low-k dielectrics is a major challenge and requires a balance between performance, reliability and cost. The present talk illustrates how the distinctive physical and chemical properties of Cu and low-k dielectrics are influencing integration schemes as well as presenting new opportunities for process equipment and metrology suppliers. Examples will include issues of wafer-scale and micro-scale Cu contamination; the impact of water vapor exposure and degassing on low-k dielectric performance and film adhesion; and the development of reactive pre-cleaning and annealing methods to deal with the non-passivating nature of the Cu surface.