AVS 47th International Symposium
    Manufacturing Science and Technology Monday Sessions
       Session MS-MoA

Invited Paper MS-MoA5
The Viability of sub-50nm CMOS Technology

Monday, October 2, 2000, 3:20 pm, Room 304

Session: Challenges in Semiconductor Manufacturing for the First Decade of the 21st Century
Presenter: G. Timp, Bell Laboratories, Lucent Technologies
Authors: G. Timp, Bell Laboratories, Lucent Technologies
J. Bude, Bell Laboratories, Lucent Technologies
F. Baumann, Bell Laboratories, Lucent Technologies
D. Muller, Bell Laboratories, Lucent Technologies
Y. Kim, Bell Laboratories, Lucent Technologies
M.L. Green, Bell Laboratories, Lucent Technologies
T. Sorsch, Bell Laboratories, Lucent Technologies
D.M. Tennant, Bell Laboratories, Lucent Technologies
R. Kleiman, Bell Laboratories, Lucent Technologies
W. Timp, Massachusetts Institute of Technology
P. Silverman, Bell Laboratories, Lucent Technologies
B.E. Weir, Bell Laboratories, Lucent Technologies
Correspondent: Click to Email
The complexity of an integrated circuit (IC), measured by the number of transistors incorporated into the circuit, is constrained by power dissipation. The viability of sub-50nm CMOS technology, which promises to incorporated nearly a billion MOS transistors into one circuit, is contingent upon the drive current performance of the MOSFET as well as the off-state leakage current. We are obliged to pursue improvements in the drive performance to derate the power supply voltage, thereby reducing power dissipation while improving reliability. The drive current of a MOSFET is dictated by both the thickness of the SiO@sub 2@ gate dielectric and by carrier scattering in the channel. Reducing the thickness of the gate oxide increases the drive current by increasing the carrier density in the channel through an increase in the gate capacitance. However, the gate leakage current due to direct, quantum mechanical tunneling through the oxide renders SiO@sub 2@ thickness' less than 1.3nm impractical because the off-state leakage current becomes intoleralbe.@footnote 1@ Consequently, the drive performance for t@sub ox@>1.3nm is limited by ballistic transport in the channel. We have shown that ballistic transport (with transmittance T>0.80) can be achieved at room temperature in a silicon MOSFET operating with transverse electric fields at the inversion layer in the semiconductor >1MV/cm, provided that the deleterious effect of interface roughness scattering is mitigated by optimizing the transverse field and minimizing the channel length and interface roughness. This optimum illustrates the futility of alternative, high @kappa@ gate dielectrics that give rise to a channel mobility less than that found at the equivalent SiO@sub 2@ thickness or operate at higher transverse fields, and indicates that a more sophisticated design of the source, drain and channel doping profiles will be required to satisfy the drive specifications. @FootnoteText@ @footnote 1@ D. Muller et al., Nature, 399 (1999) 758.