AVS 47th International Symposium
    Manufacturing Science and Technology Monday Sessions
       Session MS-MoA

Invited Paper MS-MoA3
SOI or USJ?: Laminated Electronics for "Post-Roadmap" CMOS

Monday, October 2, 2000, 2:40 pm, Room 304

Session: Challenges in Semiconductor Manufacturing for the First Decade of the 21st Century
Presenter: M.I. Current, Silicon Genesis
Authors: M.I. Current, Silicon Genesis
S.W. Bedell, Silicon Genesis
I.J. Malik, Silicon Genesis
F.J. Henley, Silicon Genesis
Correspondent: Click to Email
The many challenges that are projected in the ITRS99 study for fabrication of high-performance planar CMOS transistors on bulk Si for gate dimensions smaller than 60-50 nm (expected in year 2006-2008) clearly point to major changes in standard transistor design, materials and fabrication techniques. Various forms of laminated electronic substrates, beginning with Silicon-on-Insulator (SOI), provide a means to relax some of the process and materials constraints on bulk Si devices. SOI substrates also provide new design options, such as dual-gated channels and high-mobility buried channels. New technologies are now available to bond and cleave electronic materials layers with atomic layer control and surface roughness approaching 1 Å (RMS) without the need for CMP or other damage removal and polishing processes. The design and fabrication of complex laminated electronics "master slice" substrates, which can provide for integrated fabrication of opto-electronic circuits, will be illustrated with examples for such components as dual-gate CMOS, compliant substrates for III-V film growth and optical switching and coupling pathways.