AVS 46th International Symposium
    Plasma Science and Technology Division Thursday Sessions
       Session PS1-ThA

Invited Paper PS1-ThA1
High Fidelity Pattern Transfer

Thursday, October 28, 1999, 2:00 pm, Room 612

Session: High Fidelity Pattern Transfer
Presenter: K. Kasama, NEC Corporation, Japan
Authors: K. Kasama, NEC Corporation, Japan
K. Yoshida, NEC Corporation, Japan
N. Ikezawa, NEC Corporation, Japan
T. Uchiyama, NEC Corporation, Japan
Correspondent: Click to Email
The design rule of ULSI devices is being shrunk rapidly, now approaching to 150~130nm region. Moreover, the requirement of pattern formation fidelity, such as CD accuracy, overlay accuracy, pattern profile and so on, also becomes very strictly. For example, in the case of gate electrode formation, CD accuracy of less than ±10% is required after dry-etching, i.e., within ±15nm for 150nm devices. However, large CD fluctuation is usually generated in lithography process, and its amount reaches to CD budget. So, very tight CD control is necessary in dry-etching. In this presentation, current status of optical lithography will be introduced. Especially, we will discuss CD fluctuations induced by exposure tool stability, optical proximity effect and device topographic effect. In order to improve pattern fidelity, high NA scan exposure system, optical proximity effect correction mask and anti-reflective layer have been adopted as new lithographic techniques. Next, the resist pattern transfer by plasma process will be discussed, by mainly focusing on gate electrode formation. To suppress pattern density dependence (micro-loading effect) as well as gate oxide thickness reduction, we investigated two step etching process by using high density plasma, TCP. In a main etch step, vertical etched profile is formed under the plasma condition of high etch rate and low micro-loading, and then high selectivity etching to gate oxide is applied as a soft landing step. We have achieved good CD control of less than 10% in the 120~150nm gate formation. Moreover, we will mention about resist pattern shrinkage technique during BARC(bottom anti-reflective coating) plasma etching.