AVS 46th International Symposium
    Plasma Science and Technology Division Wednesday Sessions
       Session PS-WeM

Paper PS-WeM10
Characterization of Photoresist Trimming in a Lam TCP9400 With the Aid of a Profile Simulation

Wednesday, October 27, 1999, 11:20 am, Room 609

Session: Feature Profile Evolution
Presenter: V. Vahedi, Lam Research Corporation
Authors: V. Vahedi, Lam Research Corporation
S Lin, Lam Research Corporation, Taiwan
H.W. Chang, Lam Research Corporation
H.J. Tao, Taiwan Semiconductor Manufacturing Company
C.C. Chen, Taiwan Semiconductor Manufacturing Company
C.S. Tsai, Taiwan Semiconductor Manufacturing Company
M.S. Liang, Taiwan Semiconductor Manufacturing Company
Correspondent: Click to Email
As a result of the lithography limitations in printing photoresist lines below 0.18m, there is a growing interest in reducing the mask linewidth (in a controlled manner) using dry process tools. This process is called photoresist trimming. A typical polysilicon gate film stack for the next generation devices may include photoresist/hardmask/polysilicon/gate oxide. The advantage of photoresist trimming is that it can be done in situ and can be integrated into the process steps. In this paper, we will discuss the challenges and issues with this process. To accelerate the process development & optimization, we are using a profile simulator to understand the basic mechanisms. Typical trim processes include oxygen with other additives. Our proposed mechanisms for photoresist trimming include chemical etching, ion-enhanced etching & physical sputtering. These mechanisms are included in our profile simulation, and the simulation is calibrated with experimental data. We will show quantitative comparison between simulation and experiments. Once calibrated, the simulation can be used to predict profile changes for any line and spacing. The simulation is being used to study photoresist foot removal and CD variations between isolated and dense lines.