AVS 46th International Symposium
    Plasma Science and Technology Division Wednesday Sessions
       Session PS-WeA

Paper PS-WeA10
SiON SAC Etching Technique Using C@sub 4@F@sub 8@/CH@sub 2@F@sub 2@/Ar Plasma for 0.18µm Technology and Beyond

Wednesday, October 27, 1999, 5:00 pm, Room 609

Session: Dielectric Etching
Presenter: J.H. Kim, Hyundai Electronics Industries Co. Ltd., Korea
Authors: J.H. Kim, Hyundai Electronics Industries Co. Ltd., Korea
J.S. Yu, Hyundai Electronics Industries Co. Ltd., Korea
J.S. Na, Hyundai Electronics Industries Co. Ltd., Korea
J.W. Kim, Hyundai Electronics Industries Co. Ltd., Korea
Y.S. Seol, Hyundai Electronics Industries Co. Ltd., Korea
J.C. Ku, Hyundai Electronics Industries Co. Ltd., Korea
C.K. Ryu, Hyundai Electronics Industries Co. Ltd., Korea
S.J. Oh, Hyundai Electronics Industries Co. Ltd., Korea
S.B. Kim, Hyundai Electronics Industries Co. Ltd., Korea
S.D. Kim, Hyundai Electronics Industries Co. Ltd., Korea
I.H. Choi, Hyundai Electronics Industries Co. Ltd., Korea
Correspondent: Click to Email
A SAC technique using an oxynitride (SiON) layer as a contact oxide etch barrier has been developed for 0.18µm technology and beyond. Generally, a SAC which uses a SiN etch barrier for 0.25µm technology may exhibit some disadvantages such as wafer warpage, film lifting, transistor reliability degradation, large contact junction leakage, needs for additional anti-reflection coating (ARC) layer, and large parasitic capacitance due to its high dielectric constant. These demerits can be eliminated or improved when the SiON SAC technique is applied. But it is not easy to obtain an oxide etching process with a high selectivity to the SiON etch barrier because of oxygen component within the SiON layer. To overcome this problem, we intentionally introduced excessive Si during the SiON film deposition in order to increase the selectivity to SiON. The developed SiON layer plays the roles of ARC for wordline and bitline photo resist patterning, and side-wall spacer to build a MOS transistor as well as SAC oxide etch barrier. The contact oxide etch was done using C@sub 4@F@sub 8@/CH@sub 2@F@sub 2@/Ar in a dipole ring magnet (DRM) plasma. As the C@sub 4@F@sub 8@ flow rate increases, the oxide etch selectivity to the SiON increases but etch-stop tends to happen. In highly selective SAC oxide etching, it is very important to avoid etch-stop for a wide process window. It was reported that CH@sub 2@F@sub 2@ chemistry helps to widen the process window through its hydrogen effects.@footnote 1@ Our optimized contact oxide etch process showed the high selectivity to SiON larger than 25 and a wide process window (@>=@ 4 sccm) for the C@sub 4@F@sub 8@ flow rate. When the SiON SAC process was applied to a giga-bit DRAM of cell array, there was no short failure between conductive layers. @FootnoteText@ @footnote 1@J.H. Kim et al., The 193rd Meeting of Elecrochem.Soc., Abst. 183, 1998